Highly reproducible van der Waals integration of two-dimensional electronics on the wafer scale.

Two-dimensional (2D) semiconductors such as molybdenum disulfide (MoS2 ) have attracted tremendous interest for transistor applications. However, the fabrication of 2D transistors using traditional lithography or deposition processes often causes undesired damage and contamination to the atomically thin lattices, partially degrading the device performance and leading to large variation between devices. Here we demonstrate a highly reproducible van der Waals integration process for wafer-scale fabrication of high-performance transistors and logic circuits from monolayer MoS2 grown by chemical vapour deposition. By designing a quartz/polydimethylsiloxane semirigid stamp and adapting a standard photolithography mask-aligner for the van der Waals integration process, our strategy ensures a uniform mechanical force and a bubble-free wrinkle-free interface during the pickup/release process, which is crucial for robust van der Waals integration over a large area. Our scalable van der Waals integration process allows damage-free integration of high-quality contacts on monolayer MoS2 at the wafer scale and enables high-performance 2D transistors. The van-der-Waals-contacted devices display an atomically clean interface with much smaller threshold variation, higher on-current, smaller off-current, larger on/off ratio and smaller subthreshold swing than those fabricated with conventional lithography. The approach is further used to create various logic gates and circuits, including inverters with a voltage gain of up to 585, and logic OR gates, NAND gates, AND gates and half-adder circuits. This scalable van der Waals integration method may be useful for reliable integration of 2D semiconductors with mature industry technology, facilitating the technological transition of 2D semiconductor electronics.